1. Rajendra Prasad KV et al (2013) Layout design of 4-bit ripple carry adder using NOR and NAND logic. IJVES 4(09157)
2. Kumar KR et al (2014) A novel 3 transistor XOR gate based full adder design for VLSI application. ICRACVES-2014, 2349-0020
3. Hiremath Y (2014) A novel 8-bit carry select adder using 180 nm CMOS process technology. IJEERT, 2(6):187–194
4. Rawat K et al (2002) A low power and reduced area carry select adder. In: The 2002 45th midwest symposium on circuits and systems. MWSCAS-2002. ISSN 0-7803-7523-8/02
5. Uma R et al (2001) Area, delay and power comparison of adder topologies. VLSICS 3(1)