Neural Networks for Fast Design Space Exploration of On-Chip Interconnect Networks
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-4476-7_7
Reference14 articles.
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5. Park H et al (2020) Deep reinforcement learning-based optimal decoupling capacitor design method for silicon interposer-based 2.5-D/3-D ICs. IEEE Trans Components, Packaging Manuf Technol 10(3):467–478
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