Author:
Singh Shivam,Ojha Prakash Kumar,Asati Abhijit R.
Publisher
Springer Nature Singapore
Reference6 articles.
1. Harris D, Ho R, Wei GY, Horowitz M (1998) The Fanout-of-4 Inverter Delay Metric. Stanford University, Stanford, CA 94305
2. Sutherland I, Sproull B, Harris D (1999) In: Logical effort: design fast CMOS circuit. Morgan Kaufmann publishers
3. Raghav HS, Maheshwari S, Gupta A (2014) A comparative analysis of power & delay optimize digital logic families for high performance system design. Int J Signal Imaging Syst Eng 7(1):12–20
4. Rabaey JM, Chandrakasan A, Nikolic B (2004) Digital integrated circuits, 2nd edn. Pren-tice Hall of India Private Limited
5. Anacan RM, Bagay JL (2015) Logical effort analysis of various VLSI design algorithms. In: IEEE international conference on control system, computing and engineering, 27–29 November 2015, Penang, Malaysia
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Optimizing Energy Efficiency in a 4-bit Absolute Value Detector for High-Performance Computing;Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering;2023-11-03