Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies

Author:

Singh Shivam,Ojha Prakash Kumar,Asati Abhijit R.

Publisher

Springer Nature Singapore

Reference6 articles.

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3. Raghav HS, Maheshwari S, Gupta A (2014) A comparative analysis of power & delay optimize digital logic families for high performance system design. Int J Signal Imaging Syst Eng 7(1):12–20

4. Rabaey JM, Chandrakasan A, Nikolic B (2004) Digital integrated circuits, 2nd edn. Pren-tice Hall of India Private Limited

5. Anacan RM, Bagay JL (2015) Logical effort analysis of various VLSI design algorithms. In: IEEE international conference on control system, computing and engineering, 27–29 November 2015, Penang, Malaysia

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1. Optimizing Energy Efficiency in a 4-bit Absolute Value Detector for High-Performance Computing;Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering;2023-11-03

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