Posit Extended RISC-V Processor and Its Enhancement Using Data Type Casting
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-6634-7_40
Reference9 articles.
1. Jaiswal MK, So HK-H (2019) PACoGen: a hardware posit arithmetic core generator. IEEE Access 7:74586–74601
2. Tiwari S, Gala N, Rebeiro C, Kamakoti V (2019) PERI: a Posit enabled RISC-V core. arXiv:1908.01466v1 [cs.AR]
3. Sarka S, Velayuthan PM, Gomony MD (2019) A reconfigurable architecture for posit arithmetic. In: 22nd Euromicro conference on digital system design (DSD), Kallithea, Greece, pp 82–87. https://doi.org/10.1109/DSD.2019.00022
4. Arunkumar MV, Bhairathi SG, Hayatnagarkar HG (2020) PERC: Posit enhanced rocket chip. CARRV Valencia, Spain
5. Hou J, Zhu Y, Du S, Song S (2019) Enhancing accuracy and dynamic range of scientific data analytics by implementing Posit arithmetic on FPGA. J Sign Process Syst 91:1137–1148. https://doi.org/10.1007/s11265-018-1420-5
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