A Review on Comparative Analysis of Add-Shift Multiplier and Array Multiplier Performance Parameters-Reference-Cited by-同舟云学术

A Review on Comparative Analysis of Add-Shift Multiplier and Array Multiplier Performance Parameters

Published:2021 Issue: Volume: Page:453-461
ISSN:2662-3447
Container-title:Learning and Analytics in Intelligent Systems
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Author:

Kishore P.,Sravanthi P.,Deepthi G.,Rashmitha A.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-9293-5_41

Reference9 articles.

1. S.S. Nichat, S.J. Honade, P.V. Ingole, Design of digit serial FIR filter using shift add architecture, in 2014 International Conference on Smart Structures and Systems (ICSSS-2014) (2014), pp. 90–93

2. L. Guckert, E.E. Swartzlander, Optimized memristor-based multipliers, in IEEE Transactions on Circuits and Systems–I: Regular Papers (2016), pp. 1–13

3. A. Mittal, A. Nandi, D. Yadav, Comparative study of 16-order FIR filter design using different multiplication techniques. IET Circuits Devices Syst. 11(3), 196–200 (2017)

4. A. Mohapatra, A. Bisoyiv, Design of novel multipliers-vedic and shift-add for IEEE 754–2008 single precision floating-point unit in high speed applications, in 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) (2010), pp. 160–163

5. M. Mottaghi-Dastjerdi, A. Afzali-Kusha, M. Pedram, A low-power low-area multiplier based on shift-and-add architecture. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 17(2), 302–306 (2009)

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