Performance Enhancement of Dielectric Pocket-Based Dual-Gate FinFET

Author:

Singh Vikram,Kumar Pradeep,Mudgal Aditya

Publisher

Springer Singapore

Reference9 articles.

1. Wang X, Peterson J, Majhi P, Gardner MI, Kwong DL (2005) Impacts of gate electrode materials on threshold voltage (V/Sub th/) instability in nMOS HfO/Sub 2/Gate stacks under DC and AC stressing. IEEE Electron Device Lett 26(8):553–556

2. Mohata D, Rajamohanan B, Mayer T, Hudait M, Fastenau J, Lubyshev D, Liu AW, Datta S (2012) Barrier-engineered arsenide-antimonide heterojunction tunnel FETs with enhanced drive current. IEEE Electron Device Lett 33(11):1568–1570

3. Narang R, Saxena M, Gupta M (2014) Switching performance analyses of gGate material and gate dielectric engineered TFET architectures and impact of interface oxide charges. In: 2014 2nd international conference on devices, circuits and systems (ICDCS). IEEE, pp 1–6

4. Kang CY, Sohn C, Baek RH, Hobbs C, Kirsch P, Jammy R (2013) Effects of layout and process parameters on device/circuit performance and variability for 10 nm node FinFET technology. In: 2013 symposium on VLSI technology. IEEE, pp T90–T91

5. Colinge JP (2008) FinFETs and other multigate transistors. Springer, New York

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