A SiC MOSFET Current Balancing Technique Based on the Gate Driver with a Multi-channel Output Stage
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-4334-0_148
Reference6 articles.
1. Zeng, Z., Zhang, X., Zhang, Z.: Imbalance current analysis and its suppression methodology for parallel SiC MOSFETs with aid of a differential mode choke. IEEE Trans. Ind. Electron. 67(2), 1508–1519 (2020)
2. Zhao, C., Wang, L., Zhang, F.: Effect of asymmetric layout and unequal junction temperature on current sharing of paralleled SiC MOSFETs with Kelvin-source connection. IEEE Trans. Power Electron. 35(7), 7392–7404 (2020)
3. Zeng, Z., Zhang, X., Li, X.: Layout-dominated dynamic current imbalance in multichip power module: mechanism modeling and comparative evaluation. IEEE Trans. Power Electron. 34(11), 11199–11214 (2019)
4. Zhang, B., Wang, S.: Parasitic inductance modeling and reduction for wire-bonded half-bridge SiC multichip power modules. IEEE Trans. Power Electron. 36(5), 5892–5903 (2021)
5. Lv, J., Chen, C., Liu, B., Yan, Y., Kang, Y.: A dynamic current balancing method for paralleled SiC MOSFETs using monolithic Si-RC snubber based on a dynamic current sharing model. IEEE Trans. Power Electron. 37(11), 13368–13384 (2022)
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