Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder-Reference-Cited by-同舟云学术

Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder

Published:2020-08-15 Issue: Volume: Page:71-79
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
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Author:

Benhayoun Mhammed,Razi Mouhcine,Mansouri Anas,Ahaitouf Ali

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-6259-4_5

Reference14 articles.

1. Gallager RG (1962) Low density parity check codes. IRE Trans Inf Theor IT-8:21–28

2. MacKay DJ (1999) Good error-correcting codes based on very sparse matrices. IEEE Trans Inf Theor 45(2):399–431

3. Digital Video Broadcasting (DVB) (2009) Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), ETSI EN 302 307, V1.2.1, April 2009

4. IEEE (2006) IEEE Std. 802.16e-2005 and IEEE Std.802.16-2004/Cor1-2005

5. Shih X-Y, Chou H-R (2018) Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding. Integration. https://doi.org/10.1016/j.vlsi.2018.07.008

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