Performance of a Low-Power 6T-SRAM Cell for Energy-Efficient Leakage Reduction Using DTMOS Technique
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-7753-4_59
Reference13 articles.
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3. Assaderaghi F, Sinitsky D, Parke SA, Bokor J, Ko PK, Hu C (1997) Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI. In: IEEE Trans Electr Dev 44(3):414–422
4. Mutoh S, Douseki T, Matsuya Y, Aoki T, Shigematsu S, Yamada J (1995) 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J Solid-State Circuits 30(8):847–854
5. Kim S, Kosonocky SV, Knebel DR, Stawiasz K (2004) Experimental measurement of a novel power gating structure with intermediate power saving mode. In: Proceedings of the 2004 international symposium on low power electronics and design (IEEE Cat. No.04TH8758), pp 20–25
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