High Speed and Power Efficient Multiplier and Adder Designs for Linear Convolution
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-7753-4_16
Reference16 articles.
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2. Karuppusamy P (2019) Design and analysis of low-power. High-speed Baugh Wooley multiplier. J Electron 1(02):60–70
3. Kunchigi V, Kulkarni L, Kulkarni S (2012) High speed and area efficient Vedic multiplier. In: 2012 International conference on devices, circuits and systems (ICDCS), pp 360–364. https://doi.org/10.1109/ICDCSyst.2012.6188747
4. Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191
5. Yugandhar K, Raja VG, Tejkumar M, Siva D (2018) High performance array multiplier using reversible logic structure. In: 2018 international conference on current trends towards converging technologies (ICCTCT), pp 1–5. https://doi.org/10.1109/ICCTCT.2018.8550872
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