Power-Efficient Code Converters Using Sub-Threshold Adiabatic Logic Ultra-Low-Power Applications
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Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-33-6546-9_12
Reference19 articles.
1. Chaudhuri A, Saha M, Bhowmik M, Pradhan SN, Das S (2015) Implementation of circuit in different adiabatic logic. In: 2015 2nd IEEE international conference on electronics and communication systems (ICECS), pp 353–359
2. Chanda M, Jain S, De S, Sarkar CK (2015) Implementation of subthreshold adiabatic logic for ultralow-power application. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(12):2782–2790
3. Yadav RK, Rana AK, Chauhan S, Ranka D, Yadav K (2011) Adiabatic technique for energy efficient logic circuits design. In: 2011 IEEE international conference on emerging trends in electrical and computer technology, pp 776–780
4. Pindoo IA, Dhariwal S, Sharma R, Lata S (2018) Speed enhancement in the performance of two phase clocked adiabatic static CMOS logic circuits. In: International conference on intelligent circuits and systems (ICICS), Phagwara, India, pp 149–154
5. Grover V, Gosain V, Pandey N, Gupta K (2018) Arithmetic logic unit using diode free adiabatic logic and selection unit for adiabatic logic family. In: 5th international conference on signal processing and integrated networks (SPIN), Noida, India, pp 777–781
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