Author:
Karthik S.,Priyadarsini K.,Poovannan E.,Balaji S.
Publisher
Springer Nature Singapore
Reference10 articles.
1. S. Karthik, K. Priyadarsini, V. Jeanshilpa, VLSI systems for simultaneous in logic simulation, in International Conference on Recent Trends in Electrical, Control and Communication (RTECC) (2018), pp. 23–27. https://doi.org/10.1109/RTECC.2018.8625665
2. W.K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches, 1st edn. (Prentice Hall PTR, USA, 2008)
3. S. Karthik, S. Saravana Kumar, A review on parallel logic simulation. Int. J. Pure Appl. Math. 114(12), 191–199 (2017)
4. M.J. Sarmah, R.S. Pandey, System monitoring using the Zynq-7000 AP SoC processing system with the XADC AXI Interface. XAPP1182 (v1.0) November 18 (2013)
5. N. Kai, R. Nishinohara, H. Koide, A SIMD parallelization method for an application for LSI logic simulation, in 41st International Conference on Parallel Processing Workshops (2012), pp. 375–381. https://doi.org/10.1109/ICPPW.2012.54
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献