Parallelization of Simulated Annealing Algorithm for FPGA Placement and Routing

Author:

Rajesh Eswarawaka ,Pagadala Pavan Kumar,Eswara Reddy B.,Rao Tarun

Publisher

Springer Singapore

Reference21 articles.

1. Betz, V., Rose, J.: VPR: A new packing, placement and routing tool for FPGA research. In: International Workshop on Field Programmable Logic and Applications (1997)

2. Haldar, M., Nayak, A., Choudhary, A., Banerjee, P.: Parallel algorithms for FPGA placement. In: Proceedings of the Great Lakes VLSI Conference (2000)

3. Shi, X.: FPGA Placement Methodologies: A Survey. University of Alberta, Edmonton, Canada (2009)

4. Smith, M.J.S.: Application-specific integrated circuits. In: Proceedings of the VLSI Systems Series, June 1997

5. Chandy, J.A., Banerjee, P.: Parallel simulated annealing strategies for VLSI cell placement. In: 9th International Conference on VLSI Design (1996)

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