Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-10-5565-2_13
Reference24 articles.
1. S. Tewari, A. Biswas, A. Mallik, Study of InGaAs-channel MOSFETs for analog/mixed-signal system-on-chip applications. IEEE Electron Device Lett. 33(3), 372–374 (2012)
2. S. Tewari, A. Biswas, A. Mallik, Investigation on high-performance CMOS with pGe and n-InGaAs MOSFETs for logic applications. IEEE Trans. Nanotechnol 14(2), 275–281 (2015)
3. S. Tewari, A. Biswas, A. Mallik, Performance of CMOS with Si pMOS and asymmetric InP/InGaAs nMOS for analog circuit application. IEEE Trans. Electron Devices 62(5), 1655–1658 (2015)
4. C. Mondal, A. Biswas, 2-D compact model for drain current of fully depleted nanoscale GeOI MOSFETs for improved analog circuit design. IEEE Trans. Electron Devices 60(8), 2525–2531 (2013)
5. V. Palankovski, S. Selberherr, Micro materials modeling in MINIMOS-NT. Microsys. Technol. 7(4), 183–187 (2001). Springer
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