Fabrication and Investigation of Low-Voltage Programmable Flash Memory Gate Stack-Reference-Cited by-同舟云学术

Fabrication and Investigation of Low-Voltage Programmable Flash Memory Gate Stack

Published:2017-12-30 Issue: Volume: Page:35-49
ISSN:1876-1100
Container-title:Proceedings of the International Conference on Microelectronics, Computing & Communication Systems
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Author:

Dhavse Rasika,Prashant Kumar,Dabhi Chetan,Darji Anand,Patrikar R. M.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-5565-2_4

Reference36 articles.

1. K. Sung-Mo, L. Yusuf, S.-M. Yoo, CMOS Digital Integrated Circuits: Analysis and Design, 3rd edn. (TMH, New Delhi, India, 2003)

2. M. Jan, Rabaey, Anantha Chandrakasan, Borivoje Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Pearson Prentice-Hall, Delhi, India, 2008)

3. Datalight Inc (2008) Choosing NAND or NOR Flash Memory: Tradeoffs and Strategies. Available: http://www.datalight.com . 8 July 2008

4. Toshiba America Electronic Components, Inc. (2011). NAND vs. NOR Flash Memory Technology Overview. Available: www.mitchellcreativegroup.com . 21 May 2011

5. Jan De Blauwe, Nanocrystal nonvolatile memory devices. IEEE Trans. Nanotechnol. 1(1), 72–77 (2002)

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