1. Rony, M.W., Bhowmik, P., Myler, H.R., Mondol, P.: Short channel effects suppression in a dual-gate gate-all-around Si nanowire junctionless nMOSFET. Proc. 9th Int. Conf. Electr. Comput. Eng. ICECE 2016 538–541 (2017)
2. Input, M.S.: Impact of hot carrier degradation on MOSFET small-signal input, output, and transmission features. In: ICCDCS (2014)
3. Ghosh, S., Chattopadhyay, A., Tewari, S.: Optimization of hetero-gate-dielectric tunnel FET for label-free detection and identification of biomolecules. IEEE Trans. Electron Devices 67, 1–8 (2019)
4. Swain, S.K., Das, S.K., Biswal, S.M., Adak, S., Nanda, U., Sahoo, A.A., Navak, D., Baral, B., Tripathy, D.: Effect of high-K spacer on the performance of non-uniformly doped DG-MOSFET. Proc. 3rd Int. Conf. 2019 Devices Integr. Circuit, DevIC 510–514 (2019)
5. Kumar, V., Gupta, R., Preet, R., Singh, P., Vaid, R.: Performance analysis of double gate n-FinFET using high-k dielectric materials. Int. J. Innov. Res. Sci. Eng. Technol. 5, 13242–13249 (2016)