Comparative Analysis of Adder for Various CMOS Technologies
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-7394-1_25
Reference12 articles.
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3. Sharma, T., Sharma, K.G., Singh, B.P.: High performance full adder cell: a comparative analysis. In: TechSym 2010–Proceedings 2010 IEEE Students’ Technol. Symposium, pp. 156–160 (2010). https://doi.org/10.1109/techsym.2010.5469170
4. Chuang, P., Li, D., Sachdev, M.: Constant delay logic style. IEEE Trans. Very Large Scale Integr. Syst. 21(3), 554–565 (2013). https://doi.org/10.1109/TVLSI.2012.2189423
5. Bansal, D., Engineering,C., Singh, B.P., Engineering, C., Kumar, A.: A novel low power keeper technique for pseudo domino logic. pp. 1–6 (2015)
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