Power Optimized Domino Logic Design of a Comparator with Variable Threshold CMOS and Clock Gating
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6855-8_35
Reference10 articles.
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5. Singhal S, Mehra A, Tripathi U (2019) Power reduction in domino logic using clock gating in 16 nm CMOS technology. In: 2019 6th International conference on signal processing and integrated networks (SPIN). IEEE, pp 274–277
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