Realization of 2-D DCT Using Adder Compressor
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-0184-5_49
Reference12 articles.
1. Schiavon, T., Paim, G., Fonseca, M., Costa, E., Almeida, S.: Exploiting adder compressors for power-efficient 2-D approximate DCT realization. In: 7th Latin American Symposium on Circuits & Systems (LASCAS), pp. 383–386 (2016)
2. Bayer, F.M., Cintra, R.J.: Image compression via a fast DCT approximation. IEEE Latin Am. Trans. 8(6), 708–713 (2010)
3. Edirisuriya, A., Madanayake, A., Cintra, R.J., Bayer, F.M.: A multiplication-free digital architecture for 16 × 16 2-D DCT/DST transform for HEVC. In: 27th Convention of Electrical & Electronics Engineers in Israel (IEEEI), pp. 1–5 (2012)
4. Bayer, F.M., Cintra, R.J., Madanayake, A., Potluri, U.S.: Multiplier less approximate 4-point DCT VLSI architectures for transform block coding. Electron. Lett. 49(24), 1532–1534 (2013)
5. Potluri, U.S., Madanayake, A., Cintra, R.J., Bayer, F.M., Kulasekera, S., Edirisuriya, A.: Improved 8-point approximate DCT for image and video compression requiring only 14 additions. IEEE Trans. Circuits Syst. I: Regul. Pap. 61(6), 1727–1740 (2014)
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