Partition-Based Task Mapping for Communication Energy Minimization in 3D Network-on-Chip
Publisher
Springer Singapore
Reference18 articles.
1. Bjerregarrd T, Mahadevan M (2006, March) A survey of research and practices of network-on-chip. ACM Comput Surv 38(1):1–51
2. Katti G, Stucchi M, Meyer K, Dehaene W (2009, January) Electrical modeling and characterization of through silicon via for three-dimensional ICs. Proc IEEE 97(1):96–107
3. Karypis D, Kumar V (1998) Multilevel k-way partitioning scheme for irregular graphs. J Parallel Distrib Comput 48(1):96–129
4. Hu J, Marculescu R (2005, April) Energy- and performance-aware mapping for regular NoC architecture. IEEE Trans Comput Aided Des Integr Circuits Syst 24(4):551–562
5. Seiculescu C, Murali S, Benini L, Micheli G (2010, December) SunFloor 3D: a tool for networks on Chip topology synthesis for 3-D systems on chips. IEEE Trans Comput Aided Des Integr Circuits Syst 29(12):1987–2000