Design and Implementation of Phase Frequency Detectors for Low-Power PLL

Author:

Aneesh Bharadwaj D.,Parashar Vaishnavi S.,Dhanush T. N.,Premananda B. S.

Publisher

Springer Singapore

Reference10 articles.

1. M.K. Abdul, J.K. Binsu, Low power, high frequency, free dead zone PFD for a PLL design, in 2013 IEEE Faible Tension Faible Consommation IEEE (2013)

2. A. Tiwari, A review on design and analysis of low power PLL for digital applications. IJRASET 6, 1677–1684 (2018)

3. S.K. Garg, B. Singh, A novel design of an efficient low power phase frequency detector for delay locked loop, in 2016 IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES) (IEEE, 2016)

4. K. Arshak, O. Abubaker, E. Jafer, Design and simulation difference types cmos phase frequency detector for high speed and low jitter PLL, in Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems (2004)

5. S. Praseetha, M. Tephila, A.S. Benedict, Implementation of phase frequency detector in phase locked loop using present able modified TSPC D flip-flop. Int J. Innov. Technol. Explor. Eng. 8, 977–980 (2019)

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