Author:
Vasudeva Reddy T.,Madhava Rao K.,Yeshwanth Reddy J.,Naresh Kumar B.,Anirudh Reddy R.
Publisher
Springer Nature Singapore
Reference25 articles.
1. N. Suresh, Design, and analysis of low power full adder using GDI. Int. Electron. Electr. Comput. Syst. IJEECS 7(4) (2018)
2. E.V. Nagalakshmi, K. Kavya, Design of 4 bit ALU using modified GDI technology for power reduction. Int. Eng. Sci. Invention (IJESI) 7(2), 38–45 (2018)
3. M. Tirpathi, Low power-based manchester encoder by GDI, 2018 2nd International Conference on Inventive Systems and Control (ICISC) (Jan 2018). https://doi.org/10.1109/ICISC.2018.8398895
4. P.A. Khan, Design of 2×2 vedic multiplier using GDI technique, in International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS).(2017, Auguest). https://doi.org/10.1109/ICECDS.2017.8389786
5. K. Nehru et al., Analysis of 16-bit counter using GDI technique and CMOS logic. Int. Appl. Eng. Res. 10(6), 16121–16128 (2015)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of Serial Adder Using FinFET Based GDI Technique;2024 International Conference on Smart Systems for applications in Electrical Sciences (ICSSES);2024-05-03