Hardware-Based Parallelism Scheme for Image Steganography Speed up-Reference-Cited by-同舟云学术

Hardware-Based Parallelism Scheme for Image Steganography Speed up

Published:2020-07-31 Issue: Volume: Page:225-236
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
language:
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Author:

Seyed Dizaji Seyedeh Haleh,Zolfy Lighvan Mina,Sadeghi Ali

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-15-5148-2_20

Reference22 articles.

1. http://en.wikipedia.org/wiki/CUDA

2. M.A. Kinsy, S. Devadas, M. Pellauer, Heracles: a tool for fast RTL-based design space exploration of multicore processors. in FPGA ‘13: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey (California, USA, 2013)

3. M.A. Kinsy, M. Pellauer, S. Devadas, Heracles: fully synthesizable parameterized MIPS-based multicore system. in 21st International Conference on Field Programmable Logic and Applications (Chania, Greece, 2011)

4. S. Gupta, G. Gujral, N. Aggarwal, Enhanced least significant bit algorithm for image steganography. IJCEM Int. J. Comput. Eng. Manag. 15, 40–42 (2012)

5. S.B. Patel, S.N. Pradhan, S.U. Ambegaokar, A novel approach for implementing steganography with computing power obtained by combining CUDA and MATLAB. (IJCSIS) Int. J. Comput. Sci. Inf. Secur. 6, 133–137 (2009)

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