An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-10-1023-1_6
Reference14 articles.
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3. Halter, Jonathan P., Najm, Farid N.: Gate-level leakage power reduction method for ultra-low-power CMOS circuits. In: Proceedings of the Custom Integrated Circuits Conference, pp. 475–478 (1997)
4. Johnson, M.C., Somasekhar, D., Roy, K.: Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), 714–725 (1999)
5. Aloul, F.A., Hassoun, S., Sakallah, K.A., Blaauw, D.: Robust SAT-based search algorithm for leakage power reduction. In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2451, pp. 167–177 (2002)
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