Approximate Multiplier with Low Power Encoded Partial Products and Approximate Compressors
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-4435-1_44
Reference6 articles.
1. Natarajan, P.B., Ghosh, S.K., Karthik, R.: Low power high performance carry select adder. In: MLR Institute of Technology International Conference on Electronics, Communication and Aerospace Technology, ICECA (2017)
2. Schlachter, J., Camus, V., Palem, K.V., Enz, C.: Design and applications of approximate circuits by gate- level pruning. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(5), 1694–1702 (2017)
3. Moons, B., Verhelst, M.: Energy-efficiency and accuracy of stochastic computing circuits in emerging technologies. IEEE J. Emerg. Sel. Top. Circuits Syst. 4(4), 475–486 (2014)
4. Bhardwaj, K., Mane, P.S., Henkel, J.: Power and area-efficient approximate Wallace tree multiplier for error-resilient systems. In: Proceedings of International Symposium on Quality Electronic Design, pp. 263–269 (2014)
5. Mitchell, J.N.: Computer multiplication and division using binary logarithms. IRE Trans. Electron. Comput. EC-11(4), pp. 512–517 (1962)
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