High Stability and Low-Power Dual Supply-Stacked CNTFET SRAM Cell

Author:

Elangovan M.,Gunavathi K.

Publisher

Springer Singapore

Reference11 articles.

1. Deng J (2007) Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors. Ph.D. thesis, Stanford University

2. Dai H (2002) Carbon nanotubes: synthesis, integration, and properties. Acc Chem Res 35(12)

3. Zhang Z, Delgado-Frias JG (2014) Near-threshold CNTFET SRAM cell design with-line boosting and removed metallic CNT tolerance. IEEE Trans Nano Tech 13(2) (March 2014)

4. Rajendra Prasad S, Madhavi BK, Lal Kishore K (2012) Design of 32 nm forced stack CNTFET SRAM cell for leakage power reduction. In: International conference on computing, electronics and electrical technologies [ICCEET]

5. Birla S, Shukla NK, Pattanaik M, Singh RK (2010) Device and circuit design challenges for low leakage SRAM for ultra low power applications. Can J Electr Electron Eng 1(7):157–167

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