Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation-Reference-Cited by-同舟云学术

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Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation

Published:2018 Issue: Volume: Page:63-72
ISSN:2194-5357
Container-title:System and Architecture
language:
Short-container-title:

Author:

Sivanandam K.,Kumar P.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-8533-8_7

Reference12 articles.

1. Chen, Y.-H., Chen, J.-N., Chang, T.-Y., Lu, C.-W.: High-throughput multistandard transform core supporting MPEG/H.264/VC-1 using common sharing distributed arithmetic. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(3) (2014)

2. El-Hadedy, M., Purohit, S., Margala, M., Knapskog, S.J.: Low Latency Transpose Memory for High Throughput Signal Processing. Norwegian University of Science and Technology, Trondheim, Norway (2010)

3. Shams, A.M., Chidanandan, A., Pan, W., Bayoumi, M.A.: NEDA: a low-power high-performance DCT architecture. IEEE Trans. Signal Process. 54(3) (2006)

4. Yu, S., Swartzlander, E.E.: DCT implementation with distributed arithmetic. IEEE Trans. Comput. 50(9) (2001)

5. Hwangbo, W., Kyung, C.-M.: A Multitransform architecture for H.264/AVC high-profile coders. IEEE Trans. Multimedia 12(3) (2010)

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