Author:
Aspar Zulfakar,Rahman Nurul Huda Abd
Reference17 articles.
1. Aspar Z, Khalil-Hani M (2009) Modeling of a ladder logic processor for high performance programmable logic controller. In: Third Asia international conference on modelling & simulation, Indonesia 2009. IEEE, Bandung, pp 572–577
2. Koo KH, Gab SR, Kwon WH (1994) An architecture of the RISC processor for programmable controllers. In: Proceedings of IECON'94 - 20th annual conference of IEEE industrial electronics. IEEE, Bologna, pp 1179–1183
3. Kimy HS, Kimy DS, Changz N, Kwon WH (1999) A translation method of ladder diagram on PLC with application to a manufacturing process. In: IEEE international conference on robotics and automation. IEEE, Marriott Hotel, pp 793–798
4. Kim JI, Park J, Kwon WH (1992) Architecture of a ladder solving processor for programmable controllers. Microprocess Microsyst 16:369–379
5. Aramaki N, Shimokawa T, Kuno S, Saitoh T, Hashimoto H (1997) A new architecture for high performance programmable logic controller. In: Industrial electronics, control and instrumentation, 1997. IECON 97, 23rd international conference in 1997.IEEE, Piscataway pp 187–190