1. Li, J., Li, R., Yang, J., et al.: Low-power built-in self-test based on partial scan. Solid State Electron. Res. Prog. 25(1), 72–76 (2005)
2. Song, H., Shi, Y.: VLSI testability design technology for low-power BIST. Electron. Device 25(1), 101–104 (2002)
3. Qiu, H., Wang, C.: Pseudo-random test vector generation method based on built-in self-test. J. Huaiyin Teach. Coll.: Nat. Sci. Ed. 5(3), 212–215 (2006)
4. Zorian, Y.: A distributed BIST control scheme for complex VLSI devices. In: Proceedings of VLSI Test Symposium, pp. 4–9 (1993)
5. Girard, P.: Survey of low-power testing of VLSI circuits. Des. Test Comput. (IEEE) 19(3), 80–90 (2002)