Author:
Sahu Ganapati,Panigrahi Baibhab,Rout Shasanka Sekhar
Publisher
Springer Nature Singapore
Reference14 articles.
1. L. Garg, V. Sahula, Efficient CMOS subthreshold discharge analysis with improved stack based models in presence of parameter variation. Electron. Lett. 49(19), 644–646 (2013)
2. M.G. Priya, K. Baskaran, D. Krishnaveni, Discharge power reduction techniques in deep submicron technologies for VLSI applications. Procedia Eng. 30, 1163–1170 (2012). https://doi.org/10.1016/j.proeng.2012.01.976
3. A. Sharma, A.P. Goyal, H. Sohal, H.J. Kaur, Sleepy CMOS-sleepy stack (SC-SS): a novel high speed, area and power efficient technique for VLSI circuit design. J. Circuits Syst. Comput. 28(12), 1950197 (2019)
4. J.C. Park, V.J. Mooney, Sleepy stack discharge reduction. IEEE Trans. Very Large Scale Integr. (VLSI) Sys. 14(11), 1250–1263 (2006)
5. K. Gnana, K. Deepika, K., P.K. Mariya, D.S. Raj, Sleepy Keeper approach for power performance tuning in VLSI design. Int. J. Electron. Commun. Eng. 6(1), 17–28 (2013)