Efficient Three-Operand Binary Adder with Ladner Fischer Architecture
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-0562-7_23
Reference6 articles.
1. Reji SE, Jacob DS (2022) Three—operand binary addition using parallel prefix adders. In: IEEE 19th India council international conference (INDICON). Kochi, India, 2022, pp 1–6. https://doi.org/10.1109/INDICON56171.2022.10039889
2. Panda AK, Palisetty R, Ray KC (2020) High-speed area-efficient VLSI architecture of three-operand binary adder. IEEE Trans Circuits Syst I Regul Pap 67(11):3944–3953. https://doi.org/10.1109/TCSI.2020.3016275
3. Islam MM, Hossain MS, Hasan MK, Shahjalal M, Jang YM (2019) FPGA implementation of high-speed area-efficient processor for elliptic curve point multiplication over prime field. IEEE Access 7:178811–178826
4. Liu Z, GroBschadl J, Hu Z, Jarvinen K, Wang H, Verbauwhede I (2017) Elliptic curve cryptography with efficiently computable endomorphisms and its hardware implementations for the Internet of Things. IEEE Trans Comput 66(5):773–785
5. Liu Z, Liu D, Zou X (2017) An efficient and flexible hardware implementation of the dual-field elliptic curve cryptographic processor. IEEE Trans Ind Electron 64(3):2353–2362
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