Author:
Khorgade Manisha,Dakhole Pravin
Reference8 articles.
1. “High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures”, Amupam Chattopadhyay, Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10–14, 2008
2. Hyunchul Park, Kevin Fan, “Modulo Graph Embedding: Mapping Applications onto Coarse Grained Reconfigurable Architectures”, Proceedings of the 2006 - dl.acm.org/
3. “Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture”, Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 5, MAY 2009
4. “Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture”, Yoonjin Kim, , Rabi N. Mahapatra, Ilhyun Park, IEEE, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 10, OCTOBER 2010
5. “A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors” Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 10, OCTOBER 2008