Modified VHDL Implementation of 128-Bit Rijndael AES Algorithm by Asymmetric Keys-Reference-Cited by-同舟云学术

Modified VHDL Implementation of 128-Bit Rijndael AES Algorithm by Asymmetric Keys

Published:2023 Issue: Volume: Page:253-261
ISSN:2367-3370
Container-title:Lecture Notes in Networks and Systems
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Author:

Das Soham,Kashyap Nitesh,Raman Ashish

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-19-8563-8_24

Reference13 articles.

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3. Jun Y, Jun D, Na L, Yixiong G (2010, March) FPGA-based design and implementation of reduced AES algorithm. In: 2010 International conference on challenges in environmental science and computer engineering, vol 2. IEEE, pp 67–70

4. Deshpande AM, Deshpande MS, Kayatanavar DN (2009, June) FPGA implementation of AES encryption and decryption. In: 2009 International conference on control, automation, communication and energy conservation. IEEE, pp 1–6

5. Roy S, Das AK, Chatterjee S, Kumar N, Chattopadhyay S, Rodrigues JJ (2018) Provably secure fine-grained data access control over multiple cloud servers in mobile cloud computing based healthcare applications. IEEE Trans Industr Inf 15(1):457–468

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