FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-4713-3_27
Reference31 articles.
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5. Cherkaoui A, Fischer V, Fesquet L, Aubert A (2013) A very high speed true random number generator with entropy assessment. In: Proceedings of international workshop on cryptographic hardware and embedded systems (CHES’13). Lecture notes in computer science, vol 8086. Springer, pp 179–196
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