Design and Implementation of an Efficient IIR Filter Architecture Using Merged Delay Transformation-Reference-Cited by-同舟云学术

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Design and Implementation of an Efficient IIR Filter Architecture Using Merged Delay Transformation

Published:2021-09-10 Issue: Volume: Page:555-567
ISSN:2367-3370
Container-title:Proceedings of Sixth International Congress on Information and Communication Technology
language:
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Author:

Bujjibabu P.,Kamaraju M.,Babulu K.

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-1781-2_50

Reference15 articles.

1. Naqvi SZ, Hassan SZ, Kamal T (2016) A power consumption and area improved design of IIR decimation filters via MDT. In: Intelligent system engineering (ICISE), 15–17 Jan 2016

2. Smitha GL (2017) System generator based area reduction of IIR decimation filter. Int J Innov Res Comput Commun Eng (IJIRCCE) 5(6)

3. Rashid U, Siddiq F, Muhammad T, Jamal H (2013) Area efficient decimation filter based on MDT for wireless applications. The Nucleus 50(4):301

4. Patni A (2015) Merged delay transformed IIR down sampler filter. In: International conference on industrial instrumentation and control (ICIC), College of Engineering pune, India, 28–30 May 2015

5. Farooq U (2008) Efficient architectural transformation of multi rate recursive filters. PhD thesis, University of Engineering and Technology Texila, Pakistan

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