Energy and Area Efficient Binary-to-Gray Code Converter
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-0252-9_63
Reference12 articles.
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2. Naseri H, Timarchi S (2018) Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans Very Large Scale Integr Syst 26(8). https://doi.org/10.1109/TVLSI.2018.2820999
3. Kang S-M, Leblebici Y (2003) CMOS digital integrated circuits. Tata McGraw-Hill Education
4. Ahmad N, Rezaul Hasan SM (2013) Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate. Integr VLSI J 46(4):333–344. https://doi.org/10.1016/j.vlsi.2012.06.002
5. Rathor VS, Khandelwal S, Akashe S (2014) Domino logic topologies of OR gate with variable threshold voltage keeper. IOSRJVSP 4(4):16–22
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