Delay Analysis of Hybrid Vedic Multiplier
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-7330-6_8
Reference16 articles.
1. Ganesh Kumar G, Charishma V (2012) Design of high speed vedic multiplier using vedic mathematics techniques. Int J Sci Res Publ 2:1–5
2. Arthanto YF, Ibad SI, Adiono T (2019) High speed full custom parallel multiplier based on radix-4 booth. In: 2019 international symposium on electronics and smart devices
3. Mounica Y, Naresh Kumar K, Veeramachaneni S, Noor Mahammad S (2021) Energy efficient signed and unsigned radix 16 booth multiplier design. Comput Electr Eng. https://doi.org/10.1016/j.compeleceng.2020.106892
4. Chaudhary I, Kularia D, Choudhary R (2018) Design and comparison of high speed radix-8 and radix-16 booth’s multipliers. Int J Comput Appl (0975–8887) 181(2):6–10
5. Venkatachalam S, Adams E (2019) Design and analysis of area and power efficient approximate booth multipliers. IEEE Trans Comput 68:1–8
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