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3. Inc. www.cadence.com: Clock Domain Crossing: Closing the Loop on Clock Domain Functional Implementation Problems, Cadence Design Systems
4. Cummings, C.E.: Synthesis and Scripting Techniques for Designing Multi- Asynchronous Clock Designs. SNUG San Jose 2001. 26 (2001)
5. Cummings, C.: Verilog Nonblocking Assignments With Delays, Myths and Mysteries. Synopsys User Gr. Meet. (SNUG), Bost. (2002)