Design and Analysis of 2.4 to 3.5 GHz Low-Noise Amplifier for Sub-6 Cellular LTE/5G NR Application Using CMOS 110 nm SOI Process Technology-Reference-Cited by-同舟云学术

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Design and Analysis of 2.4 to 3.5 GHz Low-Noise Amplifier for Sub-6 Cellular LTE/5G NR Application Using CMOS 110 nm SOI Process Technology

Published:2024 Issue: Volume: Page:13-27
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:en
Short-container-title:

Author:

Khobragade Ritu D.,Vidhale Bhushan R.

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-97-0767-6_2

Reference28 articles.

1. Comer DJ, Comer DT (2004) Using the weak inversion region to optimize input stage design of CMOS op amps. IEEE Trans Circuits Syst 51(I):8–14

2. Mou S, Ma JG, Seng YK et al (2005) A modified architecture used for input matching in CMOS low-noise ampliers. IEEE Trans Circuits Syst 52(11):784–788

3. Liao CH, Chuang HR (2003) A 5.7 GHz 0.18-um CMOS gain controlled diferential LNA with current reuse for WLNA receiver. IEEE Microwave Wirel Compon Lett 13(12):526–528

4. https://sites.google.com/a/lifeden.org/nanogreen/project-updates

5. https://www.microwavejournal.com/articles/30263-g-update-standards-emerge-accelerating-5g-deployment?page=3

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