Survey on the Impact of FSM Design for High-Performance Architecture Evaluation

Author:

Sowmya K.,Bujji Babu P.,Nandan Durgesh

Publisher

Springer Singapore

Reference19 articles.

1. Ka AA, Rahman A, Mahjabeen B, Rahman M (2014) An efficient design of FSM based 32-bit unsigned high-speed pipelined multiplier using VERILOGHDL, pp 164–167

2. Kaur J, Sumit K (2016) Analysis and comparison of different multiplier. Int J Recent Innov Trends Comput Commun, ISSN 2321-816975

3. Maiti A, Chakraborty K, Sultana R, Maity S (2016) Design and implementation of 4-bit vedic multiplier. Int J Emerg Trends Sci Technol 3(5):3865–3868

4. Li Q, Liang G, Bermak A (2010) A high-speed 32-bit signed/unsigned pipelined multiplier. In: 2010 fifth IEEE international symposium on electronic design, test and applications, pp 207–211

5. Chiuchisan I, Potorac AD, Graur A (2010) Finite state machine design and VHDL coding techniques. Dev Appl Syst 75

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