Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-5950-7_37
Reference23 articles.
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3. Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of Design Automation Conference 2001, pp. 684–689. IEEE (2001)
4. De Dinechin, B.D., Van Amstel, D., Poulhiès, M., Lager, G.: Time-critical computing on a single-chip massively parallel processor. In: Proceedings of the Conference on Design, Automation & Test in Europe, p. 97. European Design and Automation Association (2014)
5. Indrusiak, L.S.: End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration. J. Syst. Architect. 60(7), 553–561 (2014)
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