1. Charles, J., Jassi, P., Ananth, N., Sadat, A., Fedorova, A.: Evaluation of the Intel Core i7 turbo boost feature. In: Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), pp. 188–197, October 2009
2. Kim, J., Papaefthymiou, M.C., Neves, J.L.: Parallelizing post placement timing optimization. In: Proceedings of IEEE IPDPS, pp. 10–19 (2006)
3. Hemani, A.: Charting the EDA roadmap. IEEE Circuits Devices Mag. 20(6), 5–10 (2004)
4. Farrahi, A.H., Hathaway, D.I., Wang, M., Sarrafiadeh, M.: Quality of EDA CAD tools: definitions, metrics and directions. In: Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 395–405, March 2000
5. Roy, J.A., Markov, I.L.: High-performance routing at the nanometer scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6), 1066–1077 (2008)