1. Graphics, M.: ModelSim Simulator.
http://www.mentor.com/products/fpga/model
(2015)
2. Hauck, S., Borriello, G.: Pin assignment for multi-FPGA systems. In: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 1994, pp. 11–13 (1994)
3. Hauck, S., Borriello, G.: Logic partition orderings for multi-FPGA systems. In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995. FPGA ’95, pp. 32–38 (1995)
4. Inagi, M., Takashima, Y., Nakamura, Y.: Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. In: International Conference on Field Programmable Logic and Applications, 2009. FPL 2009, pp. 212–217 (2009)
5. Jain, S.C., Kumar, A., Kumar, S.: Hybrid multi-FPGA board evaluation by permitting limited multi-hop routing. Des. Autom. Embed. Syst. 8(4), 309–326 (2003)