1. T. Veeramani, B. Alekhya, P. Surekha, Analysis of different CMOS adders using 90 nm and 180 nm technology. Int. J. Innov. Eng. Technol. (IJIET), 177–182 (2016). ISSN: 2319-1058
2. J. Samanta, M. Halder, B.P. De, Performance analysis of high speed low power carry look ahead adder using different logic style. Int. J. Soft Comput. Eng. 2(6), 330–336 (2013). ISSN: 2231-2307
3. S. Perri, P. Corsonello, VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. VLSI Syst. 10(5), 608–613 (2002)
4. N. Jain, P. Gour, B. Shrman, A high speed low power adder in multi output domain logic. Int. J. Sci. Res. Eng. Technol., 16–18 (2014). ISSN: 2278-0882
5. P.N.S. Sujitha, S. Shilpa, Design and analysis of carry look ahead adder using 180 nm technology. Int. J. Recent. Trends Eng. Res., 502–505 (2017). ISSN: 2455-1457