Optimized 64-bit Reversible BCD Adder for Low-power Applications and Its Comparative Study

Author:

Hemalatha K. N.,Girija S.,Sangeetha B. G.

Publisher

Springer Nature Singapore

Reference13 articles.

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2. Bennet, C.H.: Logical reversibility of computation, IBM 1. Res. Develop. 17(6), 525–532 (1973)

3. Bhuvana, B., Kanchana Bhaaskaran, V.S.: Design of reversible adders using a novel reversible BKG gate. In: Online international conference on green engineering and technologies (IC-GET), IEEE (2016)

4. Babu, H.M.H., Chowdhury, A.R.: Design of a compact reversible binary coded decimal adder circuit. Elsev. J.. Syst. Arch. 52, 272–282 (2006)

5. Mohammadi, M., Haghparast, M., Eshghi, M., Navi, K.: Minimization optimization of reversible bcd-full adder/subtractor using genetic algorithm and don,t care concept. Int. J. Quantum Inf. 7(5), 969–989 (2009)

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