Implementation of Arithmetic Logic Unit Using Area-Efficient Adder-Reference-Cited by-同舟云学术

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Implementation of Arithmetic Logic Unit Using Area-Efficient Adder

Published:2022 Issue: Volume: Page:43-51
ISSN:2524-7565
Container-title:Algorithms for Intelligent Systems
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Author:

Zade Abhishek,Singha Sumit Kumar,Talukdar Jagritee,Prathima Addanki,Mummaneni Kavicharan

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-6893-7_5

Reference10 articles.

1. Babaie, S., Sadoghifar, A., Bahar, A.N.: Design of an efficient multilayer arithmetic logic unit in quantum-dot cellular automata (QCA). IEEE Trans. Circuits Syst. II Express Briefs 66(6), 963–967 (2019). https://doi.org/10.1109/TCSII.2018.2873797

2. Kirichenko, A.F., et al.: ERSFQ 8-bit parallel arithmetic logic unit. IEEE Trans. Appl. Supercond. 29(5), 1–7 (2019). https://doi.org/10.1109/TASC.2019.2904484

3. Barla, P., Joshi, V.K., Bhat, S.: A novel low power and reduced transistor count magnetic arithmetic logic unit using hybrid STT-MTJ/CMOS circuit. IEEE Access 8, 6876–6889 (2020). https://doi.org/10.1109/ACCESS.2019.2963727

4. Stephen, B., Zvonko, V.: Fundamental of digital logic with VLSI design, 3rd edition, McGraw Hills companies. Inc (2009)

5. Balali, M., Rezai, A.: Design of low-complexity and high-speed coplanar four-bit ripple carry adder in QCA technology. Int. J. Theor. Phys. 57, 1948–1960 (2018). https://doi.org/doi.org/10.1007/s10773-018-3720-8

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1. VLSI Implementation of Accuracy Configurable Radix-4 Adder for Digital Image Processing Applications;2022 1st IEEE International Conference on Industrial Electronics: Developments & Applications (ICIDeA);2022-10-15

2. Implementation of a Low-power N-bit Hybrid Carry Select Adder with Sum-Carry Selection;2022 IEEE International Conference on Data Science and Information System (ICDSIS);2022-07-29

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