The Future of the Memory Semiconductor Industry
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_47
Reference9 articles.
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2. Giterman R, Teman A, Meinerzhagen P. Hybrid GC-eDRAM/SRAM Bitcell for robust low-power operation. IEEE Trans Circuits Syst II: Express Briefs. 2017;64(12):1362–6. https://doi.org/10.1109/TCSII.2017.2768102.
3. Panda SN, Padhi S, Phanindra V, Nanda U, Pattnaik SK, Nayak D. Design and implementation of SRAM macro unit. In: 2017 international conference on trends in electronics and informatics (ICEI), Tirunelveli, India; 2017. p. 119–23. https://doi.org/10.1109/ICOEI.2017.8300898.
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5. Gupta N, Makosiej A, Shrimali H, Amara A, Vladimirescu A, Anghel C. Tunnel FET negative-differential-resistance based 1T1C refresh-free-DRAM, 2T1C SRAM and 3T1C CAM. IEEE Trans Nanotechnol. 2021;20:270–7. https://doi.org/10.1109/TNANO.2021.3061607.
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