Performance Analysis of Data Communication Using Hybrid NoC for Low Latency and High Throughput on FPGA

Author:

Amaresh C.,Jatti Anand

Publisher

Springer Singapore

Reference14 articles.

1. Modarressi, M., et.al.: A hybrid packet-circuit switched on-chip network based on SDM. 978-3-9810801-5-5/DATE09, 2009 EDAA

2. Kuma, S.: A network on chip architecture and design methodology. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’02). IEEE (2002). 0-7695-1486-3/02

3. Lotfi-Kamran, P.: An efficient hybrid-switched network-on-chip for chip multiprocessors. IEEE Trans. Comput. 65(5), 1656–1662 (2016)

4. Shin, K.G., et al.: Investigation and implementation of hybrid switching. IEEE Trans. Comput. 45(6) (1996)

5. Agyeman, M.O., et al.: Broadening the performance of hybrid NoCs past the limitations of network heterogeneity. J. Low Power Electron. Appl. 7, 8 (2017). https://doi.org/10.3390/jlpea7020008

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