Author:
Madhura R.,Krishnappa Krutthika Hirebasur,Manasa R.,Yashaswini K. P.
Publisher
Springer Nature Singapore
Reference12 articles.
1. Synopsys (2011) Design compiler user guide
2. Cadence (2019) Genus’s user guide
3. Deshpande N et al (2020) A review on ASIC synthesis flow employing two industry standard tools. Int J Eng Res Technol 8(17):257
4. Gayathri S et al (2017) RTL synthesis of case study using design compiler. In: Proceedings of the 2017 international conference on electrical, electronics, communication, computer, and optimization techniques (ICEECCOT), pp 1–7
5. Siva Priya G et al (2019) Static timing analysis and timing violations of sequential circuits. Int J Innov Technol Explor Eng 8(7)