Optimization of InP HEMT Using Multilayered Cap and Asymmetric Gate Recess
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-1343-1_3
Reference20 articles.
1. Nguyen, L.D., Brown, A.S., Thompson, M.A., Jelloian, L.M., Larson, L.E., Matloubian, M.: 650-AA self-aligned-gate pseudomorphic Al/sub 0.48/In/sub 0.52/As/Ga/sub 0.2/In/sub 0.8/As high electron mobility transistors. IEEE Electron Device Lett. 13(3), 143–145 (1992)
2. Robin, F., Meier, H., Homan, O.J., Bachtold, W.: A novel asymmetric gate recess process for InP HEMTs. In: Conference Proceedings 14th Indium Phosphide and Related Materials Conference (Cat. No. 02CH37307), pp. 221–224 (2002)
3. Takahashi, T., et al.: Enhancement of fmax to 910 GHz by adopting asymmetric gate recess and double-side-doped structure in 75-nm-gate InAlAs/InGaAs HEMTs. IEEE Trans. Electron Devices 64(1), 89–95 (2017)
4. Cidronali, A., et al.: Ultralow DC power VCO based on InP-HEMT and heterojunction interband tunnel diode for wireless applications. IEEE Trans. Microw. Theory Tech. 50(12), 2938–2946 (2002)
5. Rosenbaum, S.E., et al.: 155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators. IEEE Trans. Microw. Theory Tech. 43(4), 927–932 (1995)
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